First, I would like to explain what is the current system of virtual memory addressing system.
The current system is called paging, which is a method of virtual memory addressing system that stores accessing information in a page table.
Page Table is a per-process data structure that manages virtual-to-physical address translations, mapping virtual page numbers to physical frame numbers. Page table is stored in the main memory.
Page table stores an array of PTE (page table entry) where each PTE contains the following information:
valid bit: indicates whether the page is valid or not.
Protection bits: organize the access rights of the page (read, write, execute).
present bit: indicates whether the page is in the physical memory or not (in the swap space, aka. disk).
dirty bit: indicates if the page has been modified or not (since the last time it was loaded into the memory).
reference bit: Aka. accessed bit. Indicates if the page has been referenced or not (accessed since last time it was loaded into memory).
The address translation requires the following steps:
Convert the virtual address to a virtual page number (VPN) and an offset.
Use the VPN and offset to access the PTE in the process’s page table.
The PTE will be at the index [VPN + offset * sizeof(PTE)] in the page table.
After the PTE is accessed, the following steps are required:
Analyze the PTE to determine if the page is valid or not; if not, raise segmentation fault.
Analyze the PTE to determine if the page is accessible or not; if not, raise protection faults.
Analyze the PTE to determine if the page is in the memory or not; if not, raise page fault.
If passed all previous checks, the physical memory location can be safely accessed.
To define a reversed process, which I would call it reverse paging, I would do the following:
Since memory physical addresses do not overlap, there is no need for per-process page table, instead we are going to use a global page table (GPT).
The global page table will be stored in memory, as an array that maps physical addresses to their corresponding processes pid.
The PTE will contain the following: valid bit, Protection bits, present bit, dirty bit, reference bit, process id, physical address.
When a process requests access to a specific physical address:
Access the GPT at the index of the physical address.
Check if the PTE is valid or not; if not, raise segmentation fault.
Check if the PTE is accessible or not; if not, raise protection fault. (The PTE[pid] is identical to the process’s pid).
Check if PTE is present or not; if present, the PTE[physical address] is identical to the requested physical address; if not; the PTE[physical address] is a disk address, fetch the page containing the requested physical address from the disk and load it into the memory.
If passed all previous checks, the physical memory location can be safely accessed.
Conclusion:
The current system is much better than the reverse paging system, because the reverse paging system requires a global page table, which is a huge data structure that requires a lot of memory space, and it is not per-process, which means that if a process is not using a specific physical address, it will still be mapped to the global page table, which is a waste of memory space.
Swapped pages need extra entries in the global page table, which is a waste of memory space.
When swapping pages in/out, the global page table needs to be updated, which is a waste of time.
Arpaci-Dusseau, R. H., & Arpaci-Dusseau, A. C. (2018). Operating systems: three easy pieces (1.01 ed.). Arpaci-Dusseau Books. Retrieved June 16, 2022, from https://pages.cs.wisc.edu/~remzi/OSTEP/.